`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 19:42:29
// Design Name: 
// Module Name: Digits_dynamic_display_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Digits_dynamic_display_tb(

    );
    
    wire a_tb, b_tb, c_tb, d_tb, e_tb, f_tb, g_tb;
    wire en3_tb, en2_tb, en1_tb, en0_tb;
    reg clk_100m;
    
    initial 
    begin
        clk_100m = 0;
        forever
        begin
            #10 clk_100m = ~clk_100m;
        end
    end
    
    Digits_dynamic_display digits_dynamic_display(
        .clk100(clk_100m),
        .AN3(4'b0000),
        .AN2(4'b0001),
        .AN1(4'b0010),
        .AN0(4'b0011),
        .EN3(en3_tb),
        .EN2(en2_tb),
        .EN1(en1_tb),
        .EN0(en0_tb),
        .a(a_tb),
        .b(b_tb),
        .c(c_tb),
        .d(d_tb),
        .e(e_tb),
        .f(f_tb),
        .g(g_tb)
    );
endmodule
